- Non layered implementation.
- Single iteration.
- Minimum sum algorithm.
- Currently supports DVB-T2 standard (short frame with effective code rate of 37/45).
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- Performs either complex vector rotation using rotating angle, or polar-to-cartesian transformation
- The input angle, complex vector ports, and the number of iterations are parametrized.
- MATLAB model is parametrized accodingly
- Fully pipelined with and initial latency of #of iterations+2
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Hard decision decoding
Fixed Complexity Sphere Decoder providing fixed throughput
Achieves close-to ML BER performance
MIMO 2x2 and 4x4
BPSK, 4-QAM, 16-QAM and 64-QAM
Efficient and optimized FPGA Architecture
Supports OFDM based systems such as the IEEE 802.16e mobile WiMAX with different Space Time Coding (STC)
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FFT Stage
- Supports radix-2, -3, -4 and -5
- Parametrized (radix, internal quantization, and FFT size)
- Used as a building block for FFTs and DFTs
- Supports all LTE, WiMAX, DVB and xDSL standards
- Configurable versatile design
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High performance BCH IP Core compliant with DVB-T2/S2 standard (Encoder and Decoder)
BCH decoder works on Galois fields GF(2M) where M = 16 or 14 and correct up to T errors where T = 10 or 12
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